Use of pulsed grounding source in a plasma reactor

ABSTRACT

A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of application Ser. No. 10/219,436,filed Aug. 14, 2002, pending, which is a continuation of applicationSer. No. 09/649,748, filed Aug. 28, 2000, now U.S. Pat. No. 6,485,572,issued Nov. 26, 2002.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to plasma reactor apparatus and processes.More specifically, the present invention relates to grounding asemiconductor substrate pedestal of a plasma reactor apparatus during aportion of a positive voltage power bias oscillation cycle to increasethe energy of ion particles of the plasma to increase the featurecharging effects regarding a substrate being etched using the plasmareactor.

2. State of the Art

High performance, lower cost, increased miniaturization of electroniccomponents, and greater density of integrated circuits are ongoing goalsof the computer industry. One commonly used technique to increase thedensity of integrated circuits involves stacking multiple layers ofactive and passive components one atop another to allow for multilevelelectrical interconnection between devices formed on each of theselayers. This multilevel electrical interconnection is generally achievedwith a plurality of metal-filled vias (“contacts”) extending throughdielectric layers that separate the component layers from one another.These vias are generally formed by etching through each dielectric layerusing etching methods known in the industry, such as plasma etching.Plasma etching is also used in the forming of a variety of features forthe electronic components of integrated circuits. In addition, verticalcapacitors may be formed by etching the features of the wall of thecapacitor in the capacitor dielectric and forming the remainingcapacitor structure around the etched dielectric. Typically, thecapacitance of the capacitor is proportional to the surface area of thewall of the capacitor etched in the dielectric material.

In plasma etching, a glow discharge is used to produce reactive species,such as atoms, radicals, and/or ions, from relatively inert gasmolecules in a bulk gas, such as a fluorinated gas, such as CF₄, CHF₃,C₂F₆, CH₂F₂, SF₆, or other freons, and mixtures thereof, in combinationwith a carrier gas, such as Ar, He, Ne, Kr, O₂, or mixtures thereof.Essentially, a plasma etching process comprises: 1) reactive species aregenerated in a plasma from the bulk gas, 2) the reactive species diffuseto a surface of a material being etched, 3) the reactive species areabsorbed on the surface of the material being etched, 4) a chemicalreaction occurs that results in the formation of a volatile byproduct,5) the byproduct is desorbed from the surface of the material beingetched, and 6) the desorbed byproduct diffuses into the bulk gas.

As illustrated in drawing FIG. 4, an apparatus 200 used in the plasmaetching process consists of an etching chamber 202 in electricalcommunication with a first AC (Alternating Current) power source 204.The etching chamber 202 further includes a pedestal 206 to support asemiconductor substrate 208 and an electrode 212 opposing the pedestal206. The electrode 212 is in electrical communication with a second ACpower source 214. The pedestal 206 has an AC power source 216. Theelectrode 212 and power source 214 may be an inductively coupled plasmasource, a microwave plasma source, or any suitable type plasma source.

In the etching chamber 202, a plasma 222 is initiated and maintained byinductively coupling AC energy from the first AC power source 204 intoan atmosphere of gases in the etching chamber 202 and the plasma 222that comprises mobile, positively and negatively charged particles andreactive species. An electric field develops in a sheath layer 224around the plasma 222, accelerating charged species (not shown) towardthe semiconductor substrate 208 by electrostatic coupling.

To assist with the etching, the potential difference between the plasma222 and the semiconductor substrate 208 can be modulated by applying anoscillating bias power from the pedestal power bias source 216 to thepedestal 206, as illustrated in drawing FIG. 5A (showing the voltageprofiles during such oscillation). During the positive voltage phase232, the substrate collects electron current from electrons that haveenough energy to cross the plasma sheath layer 224 (see drawing FIG. 4)having a plasma potential 236 (see drawing FIG. 5A). The differencebetween the instantaneous plasma potential and the surface potentialdefines the sheath potential voltage drop 238 (FIG. 5B). Since theplasma potential is more positive than the surface potential, this drophas a polarity that retards electron flow. Hence, only electrons withenergy larger than this retarding potential are collected by thesubstrate. During the negative voltage phase 234, positive ions arecollected by the substrate. These ions are accelerated by the sheathvoltage drop 238 and strike the substrate.

However, it is known that the plasma etch results, including profilemodification, can occur if the features are charged enough to modify thetrajectories of the ions and electrons that are injected into thesefeatures.

Illustrated in drawing FIG. 6 is the phenomena of electrical charging ona semiconductor device in the process of a plasma etch. A material layer244 to be etched is shown layered over a semiconductor substrate 242. Apatterned photoresist layer 246 is provided on the material layer 244for the etching of a via. During the plasma etching process, thepatterned photoresist layer 246 and material layer 244 are bombardedwith positively charged ions 248 and negatively charged electrons 252.This bombardment results in a charge distribution being developed on thepatterned photoresist layer 246 and/or the semiconductor substrate 242.This charge distribution is commonly called “feature charging.”

In order for feature charging to occur, the positively charged ions 248and the negatively charged electrons 252 must become separated from oneanother. The positively charged ions 248 and negatively chargedelectrons 252 become separated by virtue of the structures being etchedand by the differences in directionality and energy between the positiveions and electrons as they approach the feature being etched. As thestructure (in this example, a via 254) is formed by etching, the aspectratio (height to width ratio) becomes greater and greater. During plasmaetching, the positively charged ions 248 are accelerated toward thepatterned photoresist layer 246 and the material layer 244 in arelatively perpendicular manner, as illustrated in drawing FIG. 7 by thearrows adjacent positively charged ions 248. The negatively chargedelectrons 252, however, are less affected by the AC power bias source atthe semiconductor substrate 242 and, thus, move in a more randomisotropic manner, as depicted in drawing FIG. 8 by the arrows adjacentnegatively charged electrons 252. This results in an accumulation of apositive charge at a bottom 256 of via 254 because, on average,positively charged ions 248 are more likely to travel vertically towardsthe substrate 242 than are negatively charged electrons 252. Thus, anystructure with a high enough aspect ratio tends to charge morenegatively at photoresist layer 246 and an upper portion of the materiallayer 244 to a distance A (i.e., illustrated with “−” indicia) and morepositively at the via bottom 256 and the sidewalls of the via 254proximate the via bottom 256 (i.e., illustrated with “+” indicia).

As shown in drawing FIG. 7, the negatively charged sidewalls of the topof the opening deflects the positively charged ions 248 in trajectoriestowards the sidewalls. In addition, the positively charged via bottom256 also decreases the vertical component of the ion velocity andtherefore increases the relative effect of initial deflection. Thedeflection results in ion bombardment of the sidewalls 258 proximate thevia bottom 256. This can generate a portion of the etched feature with are-entrant profile, as shown in drawing FIG. 7. Such a profile can beuseful in etching a number of films. For example, a re-entrant profilein a metal film can increase alignment tolerance to shorts to adjacentcontacts by shrinking the size of the metal line as it meets the layerbelow it. In addition, a “bulge” can be etched into dielectric filmssuch as borophosphosilicate glass (BPSG) with these ions. In this case,the feature charging causes a pileup of deflected ions at a location inthe feature and some widening of the feature occurs.

As shown in drawing FIG. 8, the negatively charged photoresist layer 246and the upper portion of the material layer 244 deflect the negativelycharged electrons 252 away from entering the via 254 or slow thenegatively charged electrons 252 as they enter the via 254, both causedby charge repulsion and both of which can change the etch profile. Thistype of phenomenon is commonly known as “electron shading.”

Thus, it can be appreciated that it would be advantageous to develop anapparatus and a process of utilizing a plasma reactor that maximizes oradds a controllable effect of feature charging while using inexpensive,commercially available semiconductor device fabrication components andwithout requiring complex processing steps.

SUMMARY OF THE INVENTION

The present invention relates to an apparatus and method of reorientingelectrons generated in a plasma reactor to minimize the electrons'ability to penetrate a feature and therefore reduce charging inside thefeature.

One embodiment of the present invention comprises an etching chamber inelectrical communication with a first power source. The etching chamberfurther includes a pedestal to support a semiconductor substrate and anelectrode opposing the pedestal. The electrode is in electricalcommunication with a second power source. The pedestal is in electricalcommunication with an AC power source. The etching chamber includes asecond electrode in electrical communication with a second AC powersource. The pedestal is further in electric communication with atriggerable, high-speed switch. When triggered, the switch closes toshort the pedestal to ground. The AC power source is preferably inelectrical communication with the switch through a signal line.

As previously discussed, the potential difference between the plasma andthe semiconductor substrate can be modulated by applying an oscillatingpower from the pedestal power source to the semiconductor substrate.During the positive voltage phase, the substrate collects electroncurrent from electrons that have enough energy to cross the plasmasheath. The difference between the instantaneous plasma potential andthe surface potential defines the sheath potential drop. Since theplasma potential is more positive than the surface potential, this drophas a polarity that retards electron flow. Hence, only electrons withenergy larger than this retarding potential are collected by thesubstrate. During the negative voltage phase, positive ions arecollected by the substrate. These ions are accelerated by the sheathvoltage drop and strike the substrate. However, the present inventioncomprises the shorting of the pedestal, either in a symmetrical manneror nonsymmetrical manner, during the positive voltage phase (i.e.,during the time the negatively charged electrons flow to the wafer).This results in an increase in the electric field that retards electronflow to the wafer.

Negatively charged electrons are less affected by the DC bias at thesemiconductor substrate than are positively charged ions and, thus, movein a more random manner. However, the shorting of the pedestal,according to the present invention, alters the difference between thepotential of the plasma and potential of the semiconductor substrate fora part of the positive voltage phase. In addition, because the surfacepotential is made more negative relative to the plasma potential, onlyhigher energy electrons can overcome this increased potential barrierand reach the surface. This results in more charging and a biggerdifference between the positive voltage at the bottom of the feature andthe negative voltage at the top of the feature. This increases thefeature charging effects. In other words, the shorting of the pedestalincreases the role of feature charging on the etch results.

The triggerable, high-speed switch is preferably controlled by the poweroutput of the AC power source. Thus, when the power output of the ACpower source reaches a first predetermined level, a first signal is sentfrom the AC power source or from a sensor (not shown coupled with the ACpower source) to the triggerable, high-speed switch via the signal line.When the first signal is received by the switch, the switch closes toshort the pedestal to ground. A second signal is sent from the AC powersource or from a sensor (not shown coupled with the AC power source) toopen the switch, which discontinues the grounding of the pedestal. Thesecond signal can be sent when power output of the AC power sourcereaches a second predetermined level, or after a predetermined durationof time passes.

Thus, the present invention is capable of providing a simple andcontrollable method of effecting the quality and efficiency of plasmaetching and is easily implemented on most existing plasma reactors.

Although the examples presented are directed to the formation of anopening with a plasma etching apparatus, it is understood that thepresent invention may be utilized in a variety of feature-formation andplasma processes.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming that which is regarded as the present invention,the advantages of this invention can be more readily ascertained fromthe following description of the invention when read in conjunction withthe accompanying drawings in which:

FIG. 1 is a schematic of a plasma etching apparatus according to thepresent invention;

FIGS. 2A, 2B, and 2C are idealized graphs of an oscillating voltageprofile, current profile, and plasma sheath voltage profile of a plasmaetching apparatus pedestal according to the present invention;

FIG. 3 is a cross-sectional view of a via during an etching processaccording to the present invention;

FIG. 4 is a schematic of a prior art plasma etching apparatus;

FIGS. 5A, 5B are idealized graphs of an oscillating voltage profile andplasma sheath voltage profile of prior art plasma etching apparatuspedestal of FIG. 4;

FIG. 6 is a cross-sectional view of a via during a prior art etchingprocess that results in the phenomena on feature charging;

FIG. 7 is a cross-sectional view of a via during a prior art etchingprocess wherein feature charging results in the deflection of positivelycharged ions away from the bottom of the via and toward the sidewalls ofthe via;

FIG. 8 is a cross-sectional view of a via during a prior art etchingprocess wherein feature charging results in the deflection of negativelycharged electrons away from entering the via or slows the negativelycharged electrons as they enter the via; and

FIG. 9 is a cross-sectional view of a type of via formed by the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to drawings FIGS. 1 through 3, illustrated are variousschematics, views, and graphs of the present invention. It should beunderstood that the illustrations are not meant to be actual views ofany particular semiconductor device, but are merely idealizedrepresentations that are employed to more clearly and fully depict theformation of contact interfaces in the present invention than wouldotherwise be possible. Additionally, elements common between drawingFIGS. 1 through 3 retain the same numerical designation.

As illustrated in drawing FIG. 1, one embodiment of an etching apparatus100 of the present invention comprises an etching chamber 102 inelectrical communication with a first power source 104, such as an ACpower source, a microwave power source, or any suitable power source,etc. The etching chamber 102 further includes a pedestal 106 to supporta semiconductor substrate 108 and an electrode 112 opposing the pedestal106. The electrode 112, typically a coil or set of coils, is inelectrical communication with a second power source 114. The pedestal106 is in electrical communication with an AC pulsed power bias source116. In general, the electrode 112 can also be a plasma source driven bymicrowave power, electron cyclotron resonance power, or capacitivelycoupled rf power. Multiple frequency capacitively coupled power plasmaprocessing tools (such as a Lam Corporation, Fremont, Calif., etchercalled “EXELAN®”) are also described in drawing FIG. 1 wherein thedual-frequency supplies would simply use the switching circuit 126 (alsoreferred to as “switch 126”) on one of the two power supplies.

In the etching chamber 102, a plasma 122 is maintained by inductivelycoupling energy from the first power source 104 into the plasma 122,which comprises mobile, positively and negatively charged particles. Anelectric field, or bias voltage, develops in a sheath layer 124 aroundthe plasma 122, accelerating the electrons and ions (not shown) towardthe semiconductor substrate 108 by electrostatic coupling.

The pedestal 106 is further in electric communication with atriggerable, high-speed switch 126 interposed along an electrical pathto ground 128. When triggered, the switch 126 closes to short thepedestal 106 to ground 128. The AC power source 116 is preferably inelectrical communication with the switch 126 with a signal line 132.

As previously discussed, the potential difference between the plasma 122and the semiconductor substrate 108 can be modulated by applying anoscillating bias power from the pedestal AC pulsed power source 116 tothe semiconductor substrate 108, as illustrated in drawing FIGS. 2A, 2B,2C (showing the voltage profile for the pedestal and plasma sheath aswell as the current profile during such oscillation). During thepositive voltage phase 134, the substrate collects electron current fromelectrons that have enough energy to cross the sheath. The differencebetween the instantaneous plasma potential and the surface potentialdefines the sheath potential voltage drop 137. Since the plasmapotential is more positive than the surface potential, this drop has apolarity that retards electron flow. Hence, only electrons with energylarger than this retarding potential are collected by the substrate.During the negative voltage phase 136, positive ions are collected bythe substrate. These ions are accelerated by the sheath voltage drop andstrike the substrate. However, as also illustrated in drawing FIGS. 2A,2B, 2C, the present invention comprises the shorting of the pedestal 106during the positive voltage phase 134 (i.e., during the time theelectrons flow to the wafer) for a duration of time 138. The shorting ofthe pedestal 106 during the positive voltage phase 134 may occur eitherasymmetrically 139 or symmetrically 139′. As illustrated in drawingFIGS. 2A, 2B, 2C, with particular reference to drawing FIG. 2A, thevoltage profile has been illustrated as a displaced sine wave about thex-axis and y-axis. Although a displaced sine wave has been illustrated,the voltage could be supplied in any wave manner, displaced or not aboutthe x-axis and y-axis. Further, as illustrated specifically withreference to drawing FIG. 2A, the asymmetrical shorting or grounding 139of the pedestal 106 during the positive voltage phase 134 is shown asoccurring for a duration of time 138 being displaced along the x-axisfrom the a-axis of drawing FIG. 2A, such a-axis extending through thepeak of the positive voltage phase 134. However, the asymmetricalshorting or grounding 139′ of the pedestal 106 during the positivevoltage phase 134 could occur asymmetrically in any manner during thepositive voltage phase 134 so long as the desired etching occurs.Additionally, the symmetrical shorting or grounding 139′ of the pedestal106 during the positive voltage phase 134 is illustrated as occurringfor a duration of time 138 being displaced equally along the x-axis oneither side (left or right) from the b-axis of drawing FIG. 2A, sucha-axis extending through the peak of the positive voltage phase 134.However, the symmetrical shorting or grounding 139′ of the pedestal 106during the positive voltage phase 134 could occur symmetrically aboutthe b-axis in any manner for any duration of time 138 so long as thedesired etching occurs. Therefore, the voltage during the positive phase134 of the electrical signal to the pedestal 106 during the closing ofthe switch 126 to short or ground the pedestal 106 may occur when theclosing voltage is substantially higher, substantially lower orsubstantially equal to the voltage during the positive voltage phase 134when the switch 126 is opened. Conversely, the opening voltage duringthe positive voltage phase of the electrical signal of the switch 126 tothe pedestal 106 may occur when the opening voltage is substantiallyhigher, substantially lower, or substantially equal to the voltageduring the positive voltage phase 134 when the switch 126 is closed. Inthis manner, any desired asymmetrical or symmetrical shorting orgrounding of the pedestal 106 may occur during the positive voltagephase 134 of the electrical signal.

As previously discussed and illustrated in prior art drawing FIG. 6,negatively charged electrons 252 are less affected by the AC bias at thesemiconductor substrate than are positively charged ions and, thus, movein a more random manner, as depicted by the arrows adjacent negativelycharged electrons 252. However, the shorting or grounding of thepedestal 106, according to the present invention, alters the differencebetween the potential of the plasma 122 and potential of thesemiconductor substrate 108 for a part of the positive voltage phase134, as shown in drawing FIGS. 2A, 2B, 2C.

Referring again to drawing FIG. 1, the triggerable, high-speed switch126 is preferably controlled by the power output of the AC pulsed powersource 116. Thus, when the power output of AC pulsed power source 116reaches a first predetermined level, a first signal is sent from the ACpulsed power source 116 (or from a sensor (not shown) coupled with theAC pulsed power source 116) to the triggerable, high speed-switch 126via the signal line 132. When the first signal is received by the switch126, the switch 126 closes to a grounded position (see inset A ofdrawing FIG. 1) to short or ground the pedestal 106 to ground 128. Asecond signal is sent from the AC pulsed power source 116 (or from asensor (not shown) coupled with the AC pulsed power source 116) to openthe switch 126 to an open circuit position, as illustrated in FIG. 1,which discontinues the shorting or grounding of the pedestal 106. Thesecond signal can be sent when power output of the AC pulsed powersource 116 reaches a second predetermined level, or when a predeterminedduration of time passes. Thus, the grounding can be controlled to occurat any point during the positive voltage cycle and for any duration toachieve the desired etching results for a particular semiconductormaterial. Referring to drawing FIG. 3, illustrated in a cross-sectionalview of hole 144 being formed in a substrate 148 having a material layer146 thereon having a layer of photoresist 140 thereon. Negativelycharged electrons 142 are illustrated.

In using the present invention to etch typical dielectric material usedin a semiconductor device, for a common IPS plasma etcher, sold byApplied Materials, the etcher would operate at a power level ofapproximately 800 watts having a power level bias of approximately 700watts using a CHF₃ gas at a flow rate of approximately 22 sccm, the rooftemperature of the etcher being independently controlled, and at apressure level of approximately 20 mtorr. The roof temperature is set toapproximately 140° C. and the ring temperature to approximately 200° C.with the bias frequency in the range of 1.7+/−0.2 MHZ. Under theseconditions, the rf voltage at the wafer surface is estimated to beapproximately in the range of 300 to 400 volts AC with the plasma havinga potential below 50 volts at its peak.

In other instances, the present invention may be used to etch metal usedin semiconductor devices, such as etching conductors in semiconductordevices. During the time that the conductor is etching, there is nofeature charging. However, most metal etches finish on an insulator,including overetching. During this period, the bottom of the feature cancharge up since it is an insulator, and the effects of feature chargingcan begin. For example, the conductor profile could be made re-entrantduring the overetch if the feature charging is increased.

The present invention is particularly useful in the formation of highaspect ratio contact holes or apertures in dielectric material used insemiconductor devices. For instance, high aspect ratio contact holes orapertures in dielectric material may have a ratio of height to diameterof greater than 5:1 using the present invention.

Additionally, if desired, an aperture 254, opening 254, via 254, or hole254 may be formed having a plurality of bulges 255 therein using thepresent invention as illustrated in drawing FIG. 9. As illustrated, ahigh aspect ratio hole 254 is formed in a substrate 242 having aplurality of bulges 255 formed therein by the continual switching of thevoltage during the operation of the etcher as described herein.

For instance, during the deposition of a dielectric into a high aspectratio feature, the controlled increase in feature charging can be usedto reduce ion energy to the bottom of the feature and vary the filmdeposition rate and film properties in the feature. For example, a fillcould be made to form a bread-loaf shape of dielectric material at thetop of the feature while having a low deposition rate inside thefeature. This allows voids to be formed by increasing the featurecharging during the deposition of the dielectric material.

Thus, the present invention is capable of providing a simple andcontrollable method of affecting the quality and efficiency of plasmaetching and is easily implemented on most existing plasma reactors.Furthermore, although the examples presented are directed to theformation of a via, it is understood that the present invention may beutilized in a variety of feature formation and plasma processes.

Having thus described in detail preferred embodiments of the presentinvention, it is to be understood that the invention defined by theappended claims is not to be limited by particular details set forth inthe above description as many apparent variations thereof are possiblewithout departing from the spirit or scope thereof.

1. A plasma reactor comprising a reactor chamber including: a pedestalfor supporting a semiconductor substrate; an AC power source inelectrical communication with said pedestal; and an electrical path fromground to said pedestal including a switch, said switch being operablebetween an open position and a closed position.
 2. A plasma reactorcomprising: a reactor chamber; a first AC power source in electricalcommunication with said reactor chamber; a pedestal disposed within saidreactor chamber for supporting a semiconductor substrate thereon; anelectrode disposed within said reaction chamber and opposing saidpedestal; a second AC power source in electrical communication with saidelectrode; and an electrical path from ground to said pedestal includinga switch, said switch being operable between an open position and aclosed position.
 3. A method of operating a plasma reactor comprising:providing a plasma reactor including a pedestal for supporting asemiconductor substrate and an AC power bias source in electricalcommunication with said pedestal; providing an electrical path fromground to said pedestal including a switch, said switch being operablebetween an open position and a closed position; delivering an electricalsignal to said pedestal from said AC power source, a voltage of saidelectrical signal oscillating between a high voltage phase and a lowvoltage phase; closing said switch to ground said pedestal during saidhigh voltage phase of said electrical signal; and opening said switchduring said high voltage phase of said electrical signal after closingsaid switch.
 4. The method of claim 3, wherein said closing said switchto ground said pedestal and said opening said switch further comprise:monitoring said voltage of said high voltage phase of said electricalsignal until said voltage of said high voltage phase reaches a selectedvoltage; closing said switch to ground said pedestal for a selectedduration of time during said high voltage phase of said electricalsignal when said selected voltage is reached; and opening said switchduring said high voltage phase of said electrical signal after saidselected duration of time expires.
 5. The method of claim 3, whereinsaid closing said switch to ground said pedestal and said opening saidswitch further comprise: monitoring said voltage of said high voltagephase of said electrical signal for a first selected voltage and asecond selected voltage; closing said switch to ground said pedestalduring said high voltage phase of said electrical signal when said firstselected voltage is reached; and opening said switch during said highvoltage phase of said electrical signal when said second selectedvoltage is reached.
 6. The method of claim 5, further comprising:closing said switch to ground said pedestal during said high voltagephase of said electrical signal when said first selected voltagecomprising a substantially higher voltage than said second selectedvoltage is reached; and opening said switch during said high voltagephase of said electrical signal when a second selected voltage comprisesa substantially lower voltage than said first selected voltage isreached.
 7. The method of claim 5, further comprising: closing saidswitch to ground said pedestal during said high voltage phase of saidelectrical signal when a first selected voltage comprising asubstantially lower voltage than said second selected voltage isreached; and opening said switch during said high voltage phase of saidelectrical signal when a second selected voltage comprising asubstantially higher voltage than said first selected voltage isreached.
 8. The method of claim 5, wherein: said first selected voltageand said second selected voltage include voltages during said positivevoltage phase of said electrical signal that are substantially equal inmagnitude.
 9. The method of claim 5, wherein: said first selectedvoltage and said second selected voltage include voltages during saidpositive voltage phase of said electrical signal that are substantiallyunequal in magnitude.
 10. A method of using a plasma reactor having apedestal for supporting a semiconductor substrate and an AC power biassource in electrical communication with said pedestal and having anelectrical path from ground to said pedestal including a switch, saidswitch having an open position and a closed position, said methodcomprising: delivering an electrical signal to said pedestal from saidAC power bias source having a voltage of said electrical signaloscillating between a high voltage phase and a low voltage phase;determining a first selected voltage and a second selected voltage ofsaid voltage of said electrical signal; closing said switch to groundsaid pedestal during said high voltage phase of said electrical signalwhen said first selected voltage is reached, said first selected voltagecomprising a substantially lower voltage than a second selected voltage;and opening said switch during said high voltage phase of saidelectrical signal after closing said switch when said second selectedvoltage is reached, said second selected voltage comprising asubstantially higher voltage than said first selected voltage.
 11. Themethod of claim 10, wherein: said first selected voltage and said secondselected voltage include voltages during a positive voltage phase ofsaid electrical signal that are substantially equal in magnitude. 12.The method of claim 10, wherein: said first selected voltage and saidsecond selected voltage include voltages during a positive voltage phaseof said electrical signal that are substantially unequal in magnitude.13. A method for creating an opening in a semiconductor device on asubstrate having a material layer thereover and a photoresist layerpatterned on said material layer in a plasma reactor chamber having apedestal for supporting a semiconductor substrate and having an AC powersource connected to said pedestal, said pedestal having a switchedelectrical path to ground for the opening and the closing thereof, saidmethod comprising: generating a plasma above said semiconductorsubstrate; delivering an electrical signal to said pedestal from said ACpower source, a voltage of said electrical signal oscillating between ahigh voltage phase and a low voltage phase; monitoring said voltage ofsaid high voltage phase of said electrical signal for a first selectedvoltage and a second selected voltage; closing a switch to ground saidpedestal during said high voltage phase of said electrical signal whensaid first selected voltage is reached, said first selected voltagecomprising a substantially lower voltage than said second selectedvoltage; and opening said switch during said high voltage phase of saidelectrical signal after closing said switch when said second selectedvoltage is reached, said second selected voltage comprising asubstantially higher voltage than said first selected voltage.
 14. Themethod of claim 13, wherein: said first selected voltage and said secondselected voltage include voltages during a positive voltage phase ofsaid electrical signal that are substantially equal in magnitude. 15.The method of claim 13, wherein: said first selected voltage and saidsecond selected voltage include voltages during a positive voltage phaseof said electrical signal that are substantially unequal in magnitude.16. A method for creating a high aspect ratio opening in a semiconductordevice in a plasma reactor chamber including a pedestal for supporting asemiconductor substrate having a material layer thereover and aphotoresist layer patterned on said material layer, said photoresistlayer patterned on said material layer having at least one aperturetherein and having an AC power source connected to said pedestal, saidpedestal including a switch connected therewith for opening and closingan electrical path to ground, said method comprising: generating aplasma above said semiconductor substrate; delivering an electricalsignal to said pedestal from said AC power source, a voltage of saidelectrical signal oscillating between a high voltage phase and a lowvoltage phase; monitoring said voltage of said high voltage phase ofsaid electrical signal for a first selected voltage and a secondselected voltage; closing said switch to ground said pedestal duringsaid high voltage phase of said electrical signal when said firstselected voltage is reached, said first selected voltage comprising asubstantially lower voltage than said second selected voltage; formingat least a portion of an opening in said semiconductor substrate;opening said switch during said high voltage phase of said electricalsignal after closing said switch when said second selected voltage isreached, said second selected voltage comprising a substantially highervoltage than said first selected voltage; and forming at least anotherportion of said opening in said semiconductor substrate.
 17. The methodof claim 16, wherein: said first selected voltage and said secondselected voltage include voltages during a positive voltage phase ofsaid electrical signal that are substantially equal in magnitude. 18.The method of claim 16, wherein: said first selected voltage and saidsecond selected voltage include voltages during a positive voltage phaseof said electrical signal that are substantially unequal in magnitude.19. The method of claim 16, wherein said at least a portion of saidopening includes one of a re-entrant profile and bulge therein.
 20. Themethod of claim 16, wherein said at least a portion of said openingincludes at least one bulge therein.
 21. The method of claim 16, whereinsaid at least another portion of said opening includes one of are-entrant profile and bulge therein.
 22. The method of claim 16,wherein said at least another portion of said opening includes at leastone bulge therein.
 23. The method of claim 16, wherein said at least aportion of said opening includes at least two bulges therein.
 24. Themethod of claim 16, wherein said at least a portion of said openingincludes a plurality of bulges therein.
 25. The method of claim 16,wherein said at least a portion of said opening has an aspect ratio ofat least 5:1.